The present invention relates generally to computer memory systems, and more particularly, to methods and systems for operating a translation lookaside buffer (TLB).
A computer processor uses a translation lookaside buffer (TLB) to translate between virtual addresses and corresponding physical addresses. The TLB is typically stored in cache memory and often in the portion of the cache memory that is on the same die as the processor (e.g., L1 cache). Generally every instruction, data fetch and store accesses the TLB to fetch and/or store the correct data for the execution of each instruction. As the TLB is accessed for essentially every instruction or data fetch or store, the TLB is in the “critical path” and directly impacts the speed of execution possible by the processor.
The size of the TLB is related to the size of the main memory coupled to the processor. By way of example, a 1 Gb memory uses a TLB that can include translations between 1 Gb virtual addresses and 1 Gb physical addresses. This is referred to as the reach of the TLB. As the TLB grows larger to reach the ever larger main memory, the TLB requires more time to access, increased power consumption and larger space on the die.
In addition to direct correlations between virtual addresses and corresponding physical addresses, the TLB can also be content addressable memory (CAM) where related content is correlated.
If the desired data is not located within the then current page of main memory referenced in the currently loaded TLB entries (referred to as a TLB miss), then the TLB entry must be reloaded to include the page that actually does include the desired page of main memory. A TLB reload is “expensive” as it delays the processor in completing the current data processing operation. The TLB can also address multiple sizes of memory pages (e.g., 8 k page, 64 k page, 512 k page, 4 Mb page, etc.). As the size of the virtual memory increases, the number of TLB misses increases and TLB must therefore be TLB entries must be reloaded more often.
Unfortunately, the demand for ever-larger memory size is rapidly outpacing the reach of the TLB. In view of the foregoing, there is a need for an improved TLB and improved systems and methods of using the TLB.